Address/Data Multiplex Interface - Fujitsu FR60 Hardware Manual

4.6

Address/data Multiplex Interface

This section describes setting of the address/data multiplex interface.
■ Without External Wait (TYP[3:0] = 0100
Figure 4.6-1 shows setting of the address/data multiplex interface when there is no external wait.
Figure 4.6-1 Setting of Address/Data Multiplex Interface Without an External Wait
READ
WRITE
• Making a setting such as TYP[3:0]=01xx
interface to be set.
• If the address/data multiplex interface is set, set 8 bits or 16 bits for the data bus width (DBW[1:0] bits).
The 32-bit bus width is not supported.
• In the address/data multiplex interface, the total of 3 cycles of 2 address output cycles + 1 data cycle
becomes the basic number of access cycles.
• In the address output cycle, AS is asserted as the output address latch enable signal. However, when CS
→ RD/WR setup delay (AWR[1]) is set to "0", the multiplex address output cycle consists of only one
cycle as shown in the figure above. Since the address cannot be directly latched at the rising edge of
AS, fetch the address at the rising edge for MCLK of the cycle in which AS is asserted (Low).
• As with a normal interface, the address indicating the start of access is outputted to A[23:0] during the
time division bus cycle. Use this address if you want to use an address more than 8/16 bits in the
address/data multiplex interface.
B
MCLK
A[23:0]
AS
CSn
RD
D[31:16]
address[15:0]
WR
D[31:16]
address[15:0]
and AWR = 0008 )
H
address[23:0]
data[15:0]
data[15:0]
in the ACR register enables the address/data multiplex
B
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