Fujitsu FR60 Hardware Manual page 149

[Clearing of the timebase counter due to the device state]
All bits of the timebase counter are cleared to "0" at the same time if the device enters one of the
following states:
• Stop state
• Settings initialization reset (INIT) state
Especially in the stop state, an interval interrupt of the timebase timer may unintentionally be generated
because the timebase counter is used to measure the oscillation stabilization wait time. Before setting stop
mode, therefore, disable timebase timer interrupts to prevent the timebase timer from being used.
In any other state, timebase timer interrupts are automatically disabled because an operation initialization
reset (RST) occurs.
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Watch Timer
The watch timer is a 15-bit free-run timer that performs incremental counting in synchronization with the
32 kHz subclock.
The operation of this timer is not affected by the clock source selection or the clock division.
The watch timer is used to measure the subclock stabilization wait time and perform processing at fixed
intervals using the subclock.
The watch timer performs incremental counting while the subclock is operating and is stopped when Bit 1
(OSCD2 bit) of the standby control register (STCR) is set to1 so that the watch timer enters stop mode. To
prevent the watch timer from being stopped in stop mode, set the OSCD2 bit to "0" before the watch timer
enters stop mode so that the subclock is not stopped.
Follow the procedure below for switching the clock source from the main clock to subclock using the
watch timer:
1. Set the watch timer for the oscillation stabilization wait time. If necessary, clear all bits of the watch
timer to "0".
2. Use the watch timer to wait until the subclock is stabilized. At this time, use a watch interrupt to secure
the oscillation stabilization wait time.
3. After the subclock has been stabilized, use Bits 9 and 8 (CLKS1 and CLKS0 bits) of the clock source
register (CLKR) to switch the clock source from the main clock to subclock.
Note:
If the clock source is switched to the subclock before the subclock is stabilized, an unstable clock is
supplied and subsequent operation is unpredictable. Be sure to switch to the subclock after the
subclock has been stabilized.
For more information on the watch timer, see Section "3.12 Watch Timer".
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