Chip Select Enable Register (Cser) - Fujitsu FR60 Hardware Manual

4.2.5

Chip Select Enable Register (CSER)

This section describes the chip select enable register in detail.
■ Configuration of the Chip Select Enable Register (CSER)
The configuration of CSER is shown below:
00000680 CSE7 CSE6 CSE5 CSE4 CSE3 CSE2 CSE1 CSE0 00000001
H
This register enables or disables each chip select area.
[Bits 31 to 24] CSE[7:0] (Chip Select Area Enable: Chip select enable 0-7)
These bits are the chip select area enable bits for CS0 to CS7.
The initial value is 00000001
When "1" is written, a chip select area operates according to the settings of ASR0 to 7, ACR0 to 7, and
AWR0 to 7.
Before setting this register, be sure to make all settings required for the corresponding chip select areas.
Table 4.2-2 lists the CSE bits and corresponding CSKs.
Table 4.2-2 CSE Bits and Corresponding CSKs
Bit [24]:CSE0
Bit [25]:CSE1
Bit [26]:CSE2
Bit [27]:CSE3
Bit [28]:CSE4
Bit [29]:CSE5
Bit [30]:CSE6
Bit [31]:CSE7
31 30 29 28
, which enables only the CS0 area.
B
CSE[7:0]
0
1
CSE bit
27 26 25 24
Area control
Disable
Enable
Corresponding CSn
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
Initial value Access
at INIT at RST
00000001
R/W
B B
183