■ External Interrupt Request Level
If the request level is an edge request, a pulse width of at least three machine cycles (peripheral clock
machine cycles) is required to detect an edge.
If the request level is a level setting, and request input arrives from outside and is then cancelled, the
request to the interrupt controller remains active because a source holding circuit exists internally.
The interrupt source register must be cleared to cancel a request to the interrupt controller.
Figure 10.3-2 shows the operation that clears the source holding circuit when a level is set.
Figure 10.3-2 Clearing the Source Holding Circuit when a Level is Set
Figure 10.3-3 shows the timing of an interrupt source and interrupt request to the interrupt controller when
interrupts are enabled.
Figure 10.3-3 Interrupt Source and Interrupt Request to Interrupt Controller when Interrupts are Enabled
Interrupt request to
An NMI has priority over all other user interrupts, and cannot be masked. However, if an NMI is
activated before it is set in ILM, the CPU does not accept the NMI but only detects the NMI source. The
NMI source is then held until ILM is set to the level that allows the NMI to be accepted.
For this reason, before using an NMI, be sure to set ILM to 16 or more after a reset.
An NMI is accepted under the following conditions:
Normal: Falling edge
STOP mode: "L" level
An NMI can be used to clear stop mode. Inputting the "L" level in the stop state clears the stop state and
causes the oscillation stabilization wait time to start.
The NMI request detector has an NMI flag that is set for an NMI request and is cleared only if an interrupt
for the NMI itself is accepted or a reset occurs. Note that this bit is not readable or writable.
Figure 10.3-4 shows the NMI request detection.
(Source holding circuit)
Holds a source while it is not cleared
Becomes inactive when source F/F is cleared