Checking The Automatic Algorithm Operating Status - Fujitsu FR60 Hardware Manual

CHAPTER 17 FLASH MEMORY
17.4.2

Checking the Automatic Algorithm Operating Status

Flash memory is provided with hardware to indicate the internal operation status of
flash memory and the completion of write/erase operations in the automatic algorithm.
The automatic algorithm can check the operating status of internal flash memory using
the hardware sequence flag described below.
■ Ready/Busy Signal (RDY/BUSYX)
The flash memory uses the ready/busy signal in addition to the hardware sequence flag to indicate whether
the internal automatic algorithm is running.
The ready/busy signal is connected to the flash memory interface circuit, where it can be read via the
"RDY" bit of the flash memory control/status register.
When the value of the "RDY" bit is "0", the flash memory is executing a write or erase operation, where
new write and erase commands are not accepted. When the value of the "RDY" bit is "1", the flash memory
is in read/write or erase operation wait state.
■ Hardware Sequence Flag
The hardware sequence flag is shown below.
During half-word read
During byte read
(from odd address only)
Note
Reading in units of words is disabled. (Only use this function in FR-CPU programming mode.)
For obtaining the hardware sequence flag as data, read an arbitrary address (an odd address in byte access)
from flash memory when the automatic algorithm is executed. The data contains five validity bits which
indicate the status of the automatic algorithm.
When the automatic algorithm is executed for ROM1, specify an address in ROM1. When executed for
ROM2, specify an address in ROM2.
(In half-word and byte access)
The hardware sequence flag becomes invalid in FR-CPU ROM mode. Always use FR-CPU programming
mode and read only in half-words or bytes.
Table 17.4-2 lists the possible statuses of the hardware sequence flag.
552
15
(Undefined)
7 6
bit
DPOLL TOGGLE TLOVER
8 7
Hardware sequence flag
Hardware sequence flag
7
5 4 3
SETIMR TOGGL2
(Undefined)
0
0
2 1 0
(Undefined) (Undefined)