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If no delay is selected by setting "0", assertion of CS0 to 3 starts at the same timing that AS is asserted. If,
at this point, successive accesses are made to the same chip select area, assertion of CS0 to CS3 without
change between two access operations may continue.
If delay is specified by selecting "1", assertion of CS0 to CS3 starts when the external memory clock
MCLK output rises. If, at this point, successive accesses are made to the same chip select area, CS0 to CS3
are negated at a timing between two access operations.
If CS delay is selected, one setup cycle is inserted before asserting the read/write strobe after assertion of
the delayed CS (operation is the same as the CS → RD/WR setup setting of W01).
The address → CS delay setting works for DACK signal (basic mode) output to the same area in the same
way. DACK output in basic mode has the same waveforms as those of CS output to the same area.
[Bit 1] W01 (CS → RD/WR Setup Extension Cycle: CS → RD/WR setup)
The CS → RD/WR setup extension cycle is set to extend the period before the read/write strobe is
asserted after CS is asserted. At least one setup extension cycle is inserted before the read/write strobe is
asserted after CS is asserted.
W01
0
0 cycle
1
1 cycle
If 0 cycle is selected by setting "0", RD/WR0 to WR1/WR are output at the earliest when external memory
clock MCLK output rises just after CS is asserted. WR0 to WR1 may be delayed one cycle or more
depending on the internal bus state.
If 1 cycle is selected by setting "1", RD/WR0 to WR1 are always output 1 cycle or more later.
When successive accesses are made within the same chip select area without negating CS, a setup
extension cycle is not inserted. If a setup extension cycle for determining the address is required, set the
W02 bit and insert the address → CS delay. Since CS is negated for each access operation, the setup
extension cycle is enabled.
If the CS delay set by W02 is inserted, this setup cycle is always enabled regardless of the setting of the
W01 bit.
[Bit 0] W00 (RD/WR → CS Hold Extension Cycle: RD/WR → CS Hold Cycle)
The RD/WR → CS hold extension cycle is set to extend the period before negating CS after the read/
write strobe is negated. One hold extension cycle is inserted before CS is negated after the read/write
strobe is negated.
W00
0
0 cycle
1
1 cycle
If 0 cycle is selected by setting "0", CS0 to CS3 are negated after the hold delay after it starts on the rising
edge of external memory clock MCLK output after RD/WR0 to WR1 are negated.
If 1 cycle is selected by setting "1", CS0 to CS3 are negated one cycle later.
When making successive accesses within the same chip select area without negating CS, the hold extension
CS → RD/WR setup delay cycle
RD/WR → CS hold extension cycle
179

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