Fujitsu FR60 Hardware Manual page 285

■ Interrupt Generation Timing
Table 6.1-7 shows the timing at which interrupts are generated.
Table 6.1-7 Interrupt Generation Timing
Interrupt flag
Count direction An interrupt is generated
change flag simultaneously with setting of
(CDCF) the flag when counting starts
immediately after the counting
direction is changed.
Compare An interrupt is generated
detection flag simultaneously with setting of
(CMPF) the flag when the values of RCR
and UDCR match when up or
down counting, reloading, or
counting is initiated.
Overflow An interrupt is generated
detection flag simultaneously with setting of
(OVFF) the flag at the timing of the first
up count after the count reaches
FFFF
Underflow An interrupt is generated
detection flag simultaneously with setting of
(UDFF) the flag at the timing of the first
down count after the count
reaches 0000
Because the value of RCR is used for both the reload and compare values, the compare detection flag is set
always when reloading is performed.
If the clear function enabled, clearing occurs when up counting is performed after the values of RCR and
UDCR match during down counting.
If a read modify write instruction is issued, "1" is read.
Even when the values of RCR and UDCR match, clearing is not performed if down counting occurs or
counting is stopped after a match or if up counting occurs after the value of RCR is rewritten.
Note:
The count direction is set to down when the count is reset. Therefore, at the first up count after
resetting, CDCF is set to "1" to indicate that the counting direction has been changed.
After the up/down count register (UDCR) reaches the maximum count that the register can hold,
counting continues without a carry-over. It therefore appears that counting is continuing with the up-
down count register cleared.
The minimum pulse width at the AIN, BIN, and ZIN pins is 2.T (T stands for the peripheral clock
machine cycle).
Flag setting interrupt
.
H
.
H
Reloading
The value of RCR is transferred
to UDCR at the timing of the
first count after the count
reaches 0000 .
H
Clearing
UDCR is cleared at the
timing of the first up count
after RCR and UDCR
match. (UDCR is not
cleared for down counting).
UDCR is cleared at the
timing of the first count
after the count reaches
FFFF .
H
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