CHAPTER 9 INTERRUPT CONTROLLER
■ NMI (Non Maskable Interrupt)
An NMI (Non Maskable Interrupt) has the highest priority among the interrupt sources handled by this
Thus, an NMI is always selected if it occurs at the same time as other interrupt sources.
Occurrence of NMI
If an NMI occurs, the following information is reported to the CPU:
Interrupt level: 15 (01111
Interrupt number: 15 (0001111
Detecting an NMI
The external interrupt and NMI module set and detect an NMI. This module only generates an interrupt
level, interrupt number, and MHALTI in response to an NMI request.
Preventing a DMA transfer occurring due to an NMI
If an NMI request occurs, the MHALTI bit of the HRCL register is set to "1" to prevent DMA transfer. To
clear the state preventing DMA transfer, clear the MHALTI bit to "0" at the end of the NMI routine.