Fujitsu FR60 Hardware Manual page 170

CHAPTER 3 CPU AND CONTROL UNITS
[Bit 8] WCL (timer clear)
Writing "0" to this bit clears the main clock oscillation stabilization wait timer to 0.
Only "0" can be written to this bit. Writing "1" to this bit does not affect timer operation.
• The value read from this bit is always "1".
■ Main Clock Oscillation Stabilization Wait Timer Interrupt
If the set interval time elapses while the main clock oscillation stabilization wait timer counter is counting
with the main clock, the main clock oscillation stabilization wait interrupt request flag (WIF) is set to "1".
Then, if the interrupt request enable bit (WIE) is set to "1" (interrupt output is enabled), an interrupt request
is output to the CPU. Note that main clock oscillation stabilization wait interrupt do not occur when main
clock oscillation is stopped (see the next Item, "Operation of interval timer function") because counting is
stopped when the main clock is stopped.
To clear an interrupt request, write "0" to the WIF bit by the interrupt processing routine. Note that the WIF
bit is set at the trailing edge of the selected frequency-divide output regardless of the value of the WIE bit.
Notes:
• The WIF and WCL bits must be cleared to "0" (WIF=WCL=0) at the same time if interrupt request
output is to be enabled (WIE = 1) or the value of the WS1 and WS0 bits are to be changed after
release from the reset state.
• If the WIE bit is changed from "0" to "1" to enable interrupt output when the WIF bit is "1", an
interrupt request is output immediately.
• If a counter clear (WCL bit of WPCR is "1") and overflow of selected bits occur at the same time,
the WIF bit is not set.
■ Operation of Interval Timer Function
The main clock oscillation stabilization wait timer counter continues incremental counting while the main
clock is oscillated. When main clock oscillation stops, counting stops in the following case:
• When the WEN bit is "0"
• Counting is stopped throughout stop mode if the MB91350A is put into stop mode by stopping main
clock oscillation with Bit 0 [OSCD1 bit] of the standby control register [STCR] set to "1". To make the
main clock oscillation stabilization wait timer operate in stop mode, set the OSCD2 bit to "0" before
entry into the standby state because the OSCD1 bit is initialized to "1" at reset by an INIT request.
• When oscillation control register (OSCCR) bit 0 (OSCDS1 bit) is set to "1" in subclock mode, main
clock oscillation and timer counting are stopped.
If the counter is cleared (WCL bit is cleared to "0"), the counter starts counting from 000000
count reaches 7FFFFF
divide output selected for the interval timer is detected during incremental counting, the main clock
oscillation stabilization wait interrupt request flag (WIF) bit is set to "1". In other words, a main clock
oscillation stabilization wait timer interrupt request is generated at the selected intervals on the basis of the
cleared time.
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, the counter restarts counting from 000000H. If the trailing edge of the frequency-
H
. When the
H