CHAPTER 3 CPU AND CONTROL UNITS
Operations with a Delay Slot
This section describes operation when operations with a delay slot are specified for a
■ Branch Instructions with Delay Slot
Instructions written as follows perform a branch operation with a delay slot:
■ Operation with Delay Slot
In an operation with a delay slot, the instruction immediately following the branch instruction (this is called
the delay slot) is executed, then the instruction at the branch destination is executed.
Since an instruction in the delay slot is executed before the branch operation, the apparent execution speed
is one cycle. However, a NOP instruction must be placed in the delay slot if there is no valid instruction put
If a conditional branch instruction is used, an instruction placed in the delay slot is executed whether or not
the condition for branching is met.
If a delay branch instruction is used, the order of execution for some instructions seems to be reversed.
However, this occurs only for updating the PC and the instructions are executed in the specified order for
other operations (register update and reference, etc.)
The following is a concrete example.
1) Ri referred by the JMP:D @Ri / CALL:D @Ri instruction is not affected even though Ri is updated by
the instruction in the delay slot.
List of instructions
Delay slot ... Executed before branch