Clock Disable Register (Idbl) - Fujitsu FR60 Hardware Manual

15.2.9

Clock Disable Register (IDBL)

This section describes the clock disable register (IDBL).
■ Clock Disable Register (IDBL)
The configuration of the clock disable register (IDBL) is shown below.
[Bit 0] Clock disable bit (DBL)
This bit specifies whether to supply or stop supply of the operating clock for the I
This bit can be used in low-power consumption mode.
Value
0
1
This bit is initialized to "0" at reset.
When "1" is written to this bit, the values read from other registers become undefined except the
values read from this register (IBDL). Writing to other than this bit (this register) becomes ineffective.
Note:
When this bit is set to "1", I
463
7
Address : 00009F
-
H
R
Initial value→ 0
Supplies the clock for I
Stops supply of the clock for I
2
C immediately stops even if send and receive operation is in progress.
15.3 Explanation of I
6 5 4
- - -
R R R R
0 0 0
Function
2
C.
2 2
C. The I C line is opened.
2
C Operation
3 2 1 0
- - - DBL
R R R/W
0 0 0 0
2
C interface.