Fujitsu FR60 Hardware Manual page 292

CHAPTER 6 8/16-bit Up/Down Counters/Timer and U-Timers
[Bit 0] UTCR (U-TIMER CleaR)
Writing "0" to UTCR clears the U-TIMER to 0000
The read value is always "1".
Notes:
• In the stop state, assert the start bit UTST (started) to automatically reload data.
• In the stop state, assert both the clear bit UTCR and the start bit UTST at the same time to clear
the counter to "0" and generate an underflow in the count-down immediately after the counter is
cleared.
• During operation, the clear bit UTCR is asserted to clear the counter to "0". As a result, a short,
whisker-like pulse may be outputted in the output waveform, possibly causing the UART to
malfunction. While the output clock is being used, do not clear it using the clear bit.
• In the timer stop state, assert both bit 1 (U-TIMER start bit: UTST) and bit 0 (U-TIMER clear bit:
UTCR) of the U-TIMER control register at the same time to set bit 3 (underflow flag: UNDR) of this
register when the counter is loaded after it has been cleared. At this timing, the internal baud rate
clock is set to "H" level.
• If the device attempts to set and clear the underflow flag at the same time, the flag is set and the
clear operation becomes ineffective.
• Always write "0" to bit 4 (UTIE) and bit 2 (CLKS) of the U-TIMER control register (UTIMC).
• If the device attempts to write to and reload the data into the U-TIMER reload register at the same
time, old data is loaded into the counter. New data is loaded into the counter only in the next
reload timing.
• If the device attempts to clear and count/reload U-TIMER at the same time, the timer clear
operation takes precedence.
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(also clears the f.f. to "0").
H