Explanation Of Dtp/External Interrupt Circuit Operation - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

16.5 Explanation of DTP/External Interrupt Circuit Operation

The DTP/external interrupt circuit has an external interrupt function and a DTP function. The setting and
operation of each function are explained.
n Setting DTP/external interrupt circuit
To operate the DTP/external interrupt circuit, the setting shown in Figure 16.7 must be performed.
ICR13
bit 15 bit 14 bit 13 bit1 2 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
/ICR10
/ICR08
ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 ICS3 ICS2 ICS1 ICS0 ISE
/ICR07
/ICR06
/ICR03
EIRR
/ENIR ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
ELVR LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
DDR5/10
: Used bit
: 1 set for bit corresponding to pin used
∆
: 0 set for bit corresponding to pin used
0 : 0 set
1 : 1 set
Set the registers using the following procedure to set registers by DTP/external interrupt circuit.
(1) Disable the bits for the DTP/interrupt enable register (ENIR).
(2) Set the bits for the interrupt request level setting register (ELVR).
(3) Clear the bits for the DTP/interrupt factor register (EIRR).
(4) Enable the bits for the DTP/interrupt enable register (ENIR).
When setting the registers for the DTP/external interrupt circuit, the output of the external interrupt request
must be disabled in advance (ENIR: EN7 to EN0 = 0). Also, when enabling output of the external interrupt
request (ENIR: EN7 to EN0 = 1), the corresponding interrupt request flag bit must be cleared in advance
(EIRR: ER7 to ER0 = 0). These actions prevent from issuing the interrupt request by mistake when setting
the register.
• Switching between external interrupt function and DTP function
Switching between the external interrupt function and the DTP function is performed using the ISE bit of
the corresponding interrupt control register (ICR). When the ISE bit is 1, the EI
DTP function operate. When the ISE bit is 0, the EI
function operate.
Notes: 1. When two or more interrupt requests are assigned to one ICR register, the interrupt levels (IL2
to IL0) are shared by all interrupt requests.
2. When one interrupt request uses the EI
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
0
1
P53 P52 P51 P50
∆ ∆ ∆ ∆
Fig. 16.7 DTP/External Interrupt Circuit
2
OS, other interrupt requests cannot use it.
16-12
0
1
P03 P02 P01 P00
∆
2
OS is disabled, making only the external interrupt
IL2 IL1 IL0
When external
interrupt function
operates
When DTP
function operates
∆ ∆ ∆
2
OS is enabled, making the