Fujitsu FR60 Hardware Manual page 195

[Bits 11 to 8] W11 to 08 (Inpage Access Wait Cycle)
These bits set the number of auto-wait cycles to be inserted into the inpage access cycle during burst
access. They are valid only for burst cycles.
W11 W10
0 0
0 0
1 1
If the same value is set for the first access wait cycle and inpage access wait cycle, the access time for the
address in each access cycle is not the same. (This is because the inpage access cycle contains an address
output delay.)
[Bits 7,6] W07, 06 (Read → Write Idle Cycle)
The read → write idle cycle is set to prevent collision of read data and write data on the data bus when a
write cycle follows a read cycle. During an idle cycle, all chip select signals are negated and the data
terminals maintain the high impedance state. If a write cycle follows a read cycle or an access operation
to another chip select area occurs after a read cycle, the specified idle cycle is inserted.
W07 W06
0 0
0 1
1 0
1 1
[Bits 5 and 4] W05, 04 (Write Recovery Cycle)
The write recovery cycle is set if a device that limits the access period after write access is to be
controlled. During a write recovery cycle, all chip select signals are negated and the data pins maintain
the high impedance state.
If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted after write
access.
W05 W04
0 0
0 1
1 0
1 1
W09 W08
0 0
0 1
...
1 1
0 cycle
1 cycle
2 cycles
3 cycles
0 cycle
1 cycle
2 cycles
3 cycles
Inpage access wait cycle
Auto-wait cycle 0
Auto-wait cycle 1
...
Auto-wait cycle 15
Read → write idle cycles
Write recovery cycles
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