Fujitsu FR60 Hardware Manual page 177

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Peripheral stop register 3 (RSTOP3)
Peripheral stop register 3 controls the supply of clock signals to the I
converters.
The configuration of peripheral stop register 3 is shown below:
RSTOP3
bit
00000497
H
Bit
7
6
5
4
3
2
1
0
Notes:
• The following points regarding peripheral stop control that uses settings in these registers:
• The register of a stopped resource cannot be read from or written to. Stop supply of the clock
signal while the relevant resource is stopped.
• Writing "1" stops the supply of the clock signal to the relevant resource. As a result, the resource
cannot be activated. To use a resource that has been stopped, write "0" to the relevant bit to set
clock signal supply state, then activate the resource.
• Do not stop peripheral resources that are subject to DMA and are in the DMA enable state.
Furthermore, do not enable DMA transfer for resources that have been stopped using these bits.
7 6 5 4
- - -
Name
- (Reserved bit).
Note: Writing "1" to this bit is not allowed. When this bit is read, "0" is
- (Reserved bit).
Note: Writing "1" to this bit is not allowed. When this bit is read, "0" is
- (Reserved bit).
Note: Writing "1" to this bit is not allowed. When this bit is read, "0" is
- (Reserved bit).
Note: Writing "1" to this bit is not allowed. When this bit is read, "0" is
- (Reserved bit).
Note: Writing "1" to this bit is not allowed. When this bit is read, "0" is
ST32 0: A clock signal is supplied to the D/A converter (initial value).
1: Supply of the clock signal is stopped.
ST31 0: A clock signal is supplied to the A/D converter (initial value).
1: Supply of the clock signal is stopped.
ST30
0: A clock signal is supplied to the I
1: Supply of the clock signal is stopped.
3 2 1
- - ST32 ST31
always read.
always read.
always read.
always read.
always read.
2
C interface and the A/D and D/A
Initial value
0 at INIT at RST
00 xx
ST30
H H
2
C interface (initial value).
Access
W
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