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INDEX
Limitations on Operation with Delay Slot ............. 69
Operation with Delay Slot ................................... 68
Operation without Delay Slot .............................. 71
Delayed Interrupt
Overview of the Delayed Interrupt Module ......... 352
Register for the Delayed Interrupt Module .......... 353
Delayed Interrupt Module
Block Diagram of the Delayed Interrupt Module
.......................................................... 353
Delayed Interrupt Module Register
Delayed Interrupt Module Register (DICR: Delayed
Interrupt Module Register) ................... 354
Demand Transfer
Operation Flowchart for Demand Transfer.......... 524
Demand Transfer 2-Cycle Transfer
Demand Transfer 2-Cycle Transfer .................... 498
Demand Transfer Fly-by Transfer
Demand Transfer Fly-by Transfer ...................... 499
Demand Transfer Request
Negate Timing of the DREQ Pin Input when a
Demand Transfer Request is Stopped
.......................................................... 518
DEOP
Timing of the DEOP Pin Output ........................ 520
Detail
Details of the Interrupt Controller Registers ........ 328
Details of the Registers for the External Interrupt and
NMI Controller ................................... 344
Detailed Explanation
Detailed Explanation of the Peripheral Stop Control
Registers ............................................ 156
Detection Result Register
Detection Result Register (BSRR) ..................... 359
Device
Device Operating States.................................... 135
Device States ................................................... 134
Device Initialization
Overview of Reset (Device Initialization) ............. 94
DICR
Delayed Interrupt Module Register (DICR: Delayed
Interrupt Module Register) ................... 354
DLYI Bit of DICR............................................ 355
Direct Addressing
Direct Addressing............................................... 54
Direct Addressing Area....................................... 46
Disabling All Channels
Disabling All Channels ..................................... 512
Divide-By Rate
Initializing the Divide-By Rate .......................... 110
Setting the Divide-By Rate................................ 110
DIVR
Base Clock Division Setting Register 0
(DIVR0) ............................................. 125
626
Base Clock Division Setting Register 1
(DIVR1) ............................................ 126
DLYI Bit
DLYI Bit of DICR ........................................... 355
DMA
DMA Fly-by Transfer (I/O -> Memory)
(TYP[3:0] = 0000
IOWR = 51
) ..................................... 213
H
DMA Fly-By Transfer (Memory -> I/O)
(TYP[3:0]=0000
) ....................................... 223
IOWR=41
H
DMA Fly-by Transfer (Memory -> I/O)
(TYP[3:0] = 0000
IOWR = 51
) ..................................... 214
H
DMA Transfer and Interrupts ............................ 506
DMA Transfer Request During External Hold
......................................................... 507
DMAC (DMA Controller) .................................... 3
External Hold Request During DMA Transfer
......................................................... 507
Notes on DMA Transfer in Sleep Mode ............. 515
Overview of DMA External Interface
Operation ........................................... 529
Simultaneous Occurrence of a DMA Transfer Request
and an External Hold Request .............. 507
Suppressing DMA............................................ 506
Timing for Clearing Interrupts During DMA ...... 510
DMA External Interface
Overview of DMA External Interface
Operation ........................................... 529
DMA Fly-by Transfer
DMA Fly-by Transfer (I/O -> Memory)
(TYP[3:0]=0000
) ....................................... 222
IOWR=41
H
DMA Transfer
DMA Transfer and Interrupts ............................ 506
External Hold Request During DMA Transfer
......................................................... 507
Notes on DMA Transfer in Sleep Mode ............. 515
DMA Transfer Request
DMA Transfer Request During External Hold
......................................................... 507
Simultaneous Occurrence of a DMA Transfer Request
and an External Hold Request .............. 507
DMAC
AC Characteristics of DMAC............................ 521
Configuration of the I/O Wait Registers for DMAC
(IOWR0 to IOWR3)............................ 181
DMAC (DMA Controller) .................................... 3
Hardware Configuration of the DMAC .............. 472
Interrupts That Enable DMAC Interrupt Control
Outputs .............................................. 514
Main DMAC Functions .................................... 472
Main DMAC Operations .................................. 493
Overview of DMAC......................................... 492
Overview of the DMAC Registers ..................... 473
, AWR = 0008
, and
B
H
, AWR=0008
, and
B
H
, AWR = 0008
, and
B
H
,AWR=0008
,and
B
H

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