Fujitsu FR60 Hardware Manual page 134

CHAPTER 3 CPU AND CONTROL UNITS
[Bits 3, 2] OS1, OS0 (Oscillation Stabilization time select)
These bits set the oscillation stabilization wait time used after a reset (INIT), return from stop mode, etc.
The values written to these bits determine the oscillation stabilization wait time, which can be selected
from the four types shown in the following table.
OS1
0
0
1
1
φ: Frequency of the system base clock; in this case, twice the cycle of the source oscillation input
• These bits are initialized to "00" by a reset (INIT) generated due to INIT pin input. If both resets (INIT)
generated due to INIT and HST pin input are valid, these bits are initialized to "11".
• These bits are readable and writable.
[Bit 1] OSCD2 (OSCillation Disable mode for XIN2)
This bit controls stopping of the sub-oscillation input (XIN2) in stop mode.
Value
0
1
• This bit is initialized to "1" by a reset (INIT).
• This bit is readable and writable.
[Bit 0] OSCD1 (OSCillation Disable mode for XIN1)
This bit controls stopping of main oscillation input (XIN1) in stop mode.
Value
0
1
• This bit is initialized to "1" by a reset (INIT).
• This bit is readable and writable.
116
Oscillation stabilization
OS0
wait time
φ x 2 1
0
(initial value)
φ x 2 11
1
φ x 2 16
0
φ x 2 22
1
Not stopping the sub-oscillation in stop mode
Stopping the sub-oscillation in stop mode (initial value)
Main oscillation does not stop in stop mode.
Main oscillation stops in stop mode (initial value).
If the source oscillation is
12.5 MHz
0.32 [µs]
328 [µs]
10.5 [ms]
671 [ms]
Explanation
Explanation
If the subclock is
32 kHz
120 [µs]
123 [ms]
3.9 [s]
251 [s]