Fujitsu FR60 Hardware Manual page 357

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Sequence
Figure 9.3-2 shows an INTC-2 interrupt level that is higher than the one set in the HRCL register.
RUN
CPU
Bus access request
DHREQ
DHACK
IRQ
LEVEL
MHALTI
If an interrupt request occurs, the interrupt level changes. If the interrupt level is higher than the level
defined in the HRCL register, MHALTI becomes active for DMA. This causes DMA to cancel an access
request and the CPU to return from the hold state to perform the interrupt processing.
Figure 9.3-3 shows the INTC-2 interrupt levels when there are multiple interrupts.
Figure 9.3-3 INT-C3 Interrupt Levels (HRCL < ICR [interrupt I] < ICR [interrupt II])
RUN
CPU
Bus access request
DHREQ
DHACK
IRQ1
IRQ2
LEVEL
MHALTI
[Example of interrupt routine]
(1), (3) Interrupt source clear
to
(2), (4) RETI
In the above example, while interrupt routine I is being executed, an interrupt with a higher priority
occurs.
While the interrupt with a higher level than the level in the HRCL register occurs, DHREQ is low.
Note:
Be especially careful about the relationship between interrupt levels defined in the HRCL register
and ICR.
Figure 9.3-2 Interrupt Level (HRCL < ICR) [LEVEL]
Bus hold Interrupt processing
(1)
Bus hold Interrupt I
(2)
Interrupt Interrupt
processing II processing I
(3) (4) (1)
Bus hold
(DMA transfer)
Example of
interrupt routine
(1) Interrupt
source clear
to
(2) RETI
Bus hold
(DMA transfer)
(2)
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