Fujitsu FR60 Hardware Manual page 655

Setting of CS -> RD/WR Setup and of RD/WR -> CS
Hold (TYP[3:0]=0000
.......................................................... 212
RDY
Ready/Busy Signal (RDY/BUSYX)................... 552
Reactivation
When Reactivation is Disabled .................. 315, 317
Read
Read/Reset Command ...................................... 549
Read -> Write Timing
Read -> Write Timing
(TYP[3:0]=0000
Reading
Reading from the Prefetch Buffer ...................... 220
Reading the I/O Map ........................................ 582
Reading/Resetting Flash Memory ...................... 558
Ready
Ready/Busy Signal (RDY/BUSYX)................... 552
REALOS
Bit Search Module (Used by REALOS) ................. 3
Receive Data
Example of Receive Data.................................. 469
Recommended ADCT Register
Recommended ADCT Register Value ................ 374
Register
0 Detection Data Register (BSD0) ..................... 358
1 Detection Data Register (BSD1) ..................... 358
10-bit Slave Address Mask Register (ITMK) ...... 458
10-bit Slave Address Register (ITBA)................ 457
16-bit Free-running Timer Registers .................. 279
16-bit Reload Register (TMRLR) ...................... 291
16-bit Reload Timer Registers ........................... 287
16-bit Timer Register (TMR) ............................ 291
7-bit Slave Address Mask Register (ISMK) ........ 461
7-bit Slave Address Register (ISBA).................. 460
8-bit D/A Converter Registers ........................... 380
A/D Converter Registers................................... 366
Address Register Specifications......................... 503
Base Clock Division Setting Register 0
(DIVR0)............................................. 125
Base Clock Division Setting Register 1
(DIVR1)............................................. 126
Bit Configuration of Enable Interrupt Request
Register (ENIRn) ................................ 345
Bit Configuration of External Level Register (ELVRn)
.......................................................... 347
Bit Configuration of the Control Status Register
(ADCS1)............................................ 367
Bit Configuration of the Control Status Register
(ADCS2)............................................ 370
Bit Configuration of the Conversion Time Setting
Register (ADCT) ................................ 373
Bit Configuration of the External Interrupt Request
Register (EIRRn) ................................ 346
,AWR=000B )
B H
).......... 206
,AWR=0048
B H
Bit Configuration of the Hold Request Cancellation
Request Register (HRCL) .....................331
Bit Configuration of the Interrupt Control Register
(ICR)..................................................329
Bit Search Module Registers..............................357
Bus Control Register (IBCR) .............................448
Bus Status Register (IBSR)................................445
CCR (Condition Code Register) ...........................58
Change Point Detection Data Register (BSDC)
..........................................................359
Clock Control Register (ICCR) ..........................455
Clock Disable Register (IDBL) ..........................463
Clock Source Control Register (CLKR) ..............120
Compare Register (OCCP0 to OCCP7)...............434
Configuration of Area Configuration Registers 0 to 7
(ACR0 to ACR7).................................169
Configuration of ASR0 to ASR3
(Area Select Registers).........................168
Configuration of AWR0 to AWR3
(Area Wait Registers)...........................175
Configuration of General Control Register 10
..........................................................310
Configuration of General Control Register 20
..........................................................313
Configuration of Interrupt Control Register (ICR)
............................................................75
Configuration of PPG Cycle Setting Register
(PCSR) ...............................................307
Configuration of PPG Duty Setting Register
(PDUT) ..............................................308
Configuration of PPG Timer Register (PTMR)
..........................................................309
Configuration of the Chip Select Enable Register
(CSER)...............................................183
Configuration of the Flash Control/Status Register
(FLCR) (CPU Mode) ...........................540
Configuration of the Flash Memory Wait Register
(FLWC)..............................................543
Configuration of the I/O Wait Registers for DMAC
(IOWR0 to IOWR3) ............................181
Configuration of the Terminal and Timing Control
Register (TCR) ....................................184
Configurations of Control Status Registers..........303
Control Status Register (TMCSR) ......................289
Correspondence between the Memory Space Area and
Peripheral Resource Registers ...............583
Counter Control Register High/Low ch0
(CCR H/L ch0)....................................252
Counter Control Register High/Low ch1
(CCR H/L ch1)....................................256
Counter Status Register 0/1 (CSR0/1).................256
DACR0 (D/A Control Register 0) ......................383
DACR1 (D/A Control Register 1) ......................383
DACR2 (D/A Control Register 2) ......................383
DADR0 (D/A Data Register 0) ..........................382
DADR1 (D/A Data Register 1) ..........................382
DADR2 (D/A Data Register 2) ..........................382
INDEX
637