CHAPTER 3 CPU AND CONTROL UNITS
■ SCR (System Condition Code Register)
The configuration of the system condition code register (SCR) is shown below:
[Bits 10 and 9] Step division flag
These bits hold the intermediate data when step division is executed.
Do not change these bits during step division. To execute other processing during a step division, save
and restore the value of the PS register to ensure that the step division is restarted.
The initial value after reset is undefined.
When the DIVOS instruction is executed, the multiplicand and divisor are accessed and this flag is set.
When the DIV0U instruction is executed, this flag is cleared.
DIV0S/DIV0U command and user interruption/NMI simultaneous receipt;
Do not perform any process desiring D0/D1 bit of the PS resister before the EIT branch in the EIT
When a halt caused by break, step, etc. occurs right before the DIV0S/DIV0U command, the D0/D1 bit
of the PS register may not display a valid value.
Calculation result, however, will be valid after recovery.
[Bit 8] Step trace trap flag
This bit specifies whether the step trace trap is to be enabled.
Reset initializes this bit to "0".
The step trace trap function is also used by emulators. When being used by an emulator, this function
cannot be used in a user program.
The step trace trap is disabled.
The step trace trap is enabled.
All user NMIs and user interrupts are prohibited.