Fujitsu FR60 Hardware Manual page 247

■ Acquiring the Bus Right
Figure 4.9-2 shows setting of acquiring the bus right.
• Setting "1" for the BREN bit of the TRC register enables bus arbitration by BRQ/BGRNT to be
performed.
• When the bus right is released, the pin is set to high impedance and then BGRNT is asserted one cycle
later.
• When the bus right is acquired, BGRNT is negated and then each pin is activated one cycle later.
• CSn is set to high impedance only if the SREN bit in the ACR0 to 7 registers is set.
• If all areas enabled by the CSER register are shared (the SREN bit of the ACR register is "1"), AS,
BAA, RD, WR, and WR0 to WR3 are set to high impedance.
Figure 4.9-2 Setting of Acquiring the Bus Right
MCLK
A23 to A0
AS
CSn
WR
D31 to D16
BRQ
BGRNT
1 cycle
229