Fujitsu FR60 Hardware Manual page 516

CHAPTER 16 DMA CONTROLLER (DMAC)
Figure 16.3-1 shows an example of burst transfer.
Transfer request ( edge)
Bus operation
Transfer count
Transfer end
■ Burst Fly-by Transfer
A burst fly-by transfer has the same features as a 2-cycle transfer except that the transfer area can only be
external areas, and the transfer unit is read (memory → I/O) or write (I/O → memory) only.
Table 16.3-2 lists the specifiable transfer addresses for burst fly-by transfer.
Table 16.3-2 Specifiable Transfer Addresses for Burst Fly-by Transfer
Transfer source addressing
Specification not required (invalid)
■ Demand Transfer 2-Cycle Transfer
A demand transfer sequence is generated only if "H" level or "L" level of an external pin is selected as a
transfer request. (Select the level with IS[3:0] of DMACA.)
[Features of a continuous transfer]
• Each transfer operation of a transfer request is checked. While the external input level is within the
range of the specified transfer request levels, transfer is performed continuously without the request
being cleared. If the external input changes, the request is cleared and the transfer stops at the transfer
boundary. This operation is repeated for the number of times specified by the transfer count.
• Otherwise, operations are the same as those of a burst transfer.
Figure 16.3-2 shows an example of demand transfer.
Transfer request ("H" level)
Bus operation
Transfer count
Transfer end
498
Figure 16.3-1 Example of Burst Transfer
CPU
Figure 16.3-2 Example of Demand Transfer
CPU SA
(Example of demand transfer where demand transfer is started by "H" level detection at an
external pin, the number of blocks is "1", and the transfer count is "3".)
DA SA SA DA
SA DA
4 3 2
Direction
None
DA SA DA
CPU
32
SA DA CPU
1 0
Transfer destination addressing
External area
SA DA
1 0