Fujitsu FR60 Hardware Manual page 237

■ Optional Clear and Temporary Stopping of a Prefetch Access
Setting "1" for the PSUS bit of the TCR register temporarily stops a prefetch. The prefetch can be restarted
by setting the PSUS bit to "0". At this point, the contents of the buffer are retained if no error occurs or a
buffer clear such as occurs when the PCLR bit is set does not occur.
Setting "1" for the PCLR bit of the TCR register completely clears the prefetch buffer. Clear the buffer by
setting the PSUS bit when prefetch is interrupted.
Prefetch is temporarily stopped for the minimum unit (64K bytes) of the boundary=chip select area where
the high-order 16 bits of an address change. If the boundary is crossed, first a buffer read error occurs and
then prefetch starts in a new area.
■ Unit for One Prefetch Access Operation
The unit for one prefetch access operation is determined by the DBW bits (bus width) and BST bits (burst
length) of the ACR register.
Prefetch access always occurs with the full size of the bus width specified by the DBW bits and access for
the count of the burst length set by the BST bits in one access operation is performed. That is, if any value
other than 00
mind whether ROM/RAM is conformable and enough access time is applicable. (Set an appropriate value
bits W15-08 bits of the AWR register).
During burst access, successive accesses occur only within the address boundary that is determined by the
burst length. Thus, if the boundary is crossed, for example, 4 bytes of free space are available in the buffer,
these 4 bytes cannot be accessed in one operation (If the prefetch buffer starts at xxxxxx0E
free space are available in the buffer, and two bursts are set even though the bus width is 16 bits, only 2
bytes, xxxxxx0E
Examples:
• Area whose bus width is set to 16 bits and whose burst length is set to "2"
The amount of data read into the buffer in one prefetch operation is 4 bytes. In this case, prefetch access
is delayed until 4 bytes of free space are available in the prefetch buffer.
• Area whose bus width is set to 8 bits and whose burst length is set to "8"
The amount of data read into the buffer in one prefetch operation is 8 bytes. In this case, prefetch access
is delayed until 8 bytes of free space are available in the prefetch buffer.
■ Burst Length Setting and Prefetch Efficiency
If requests for external bus access, other than prefetch access, to or errors in the prefetch buffer occur
during one operation of prefetch access as explained in the previous bullet, "Unit for One Prefetch Access
Operation," these access requests must wait until access to the prefetch buffer that is being executed is
completed.
Thus, if the burst length is too long, the efficiency and reaction of bus access other than prefetch may be
degraded. If, on the other hand, the burst length is set to "1", many read cycles may be wasted even if burst/
page access memory is connected because single access is always performed.
If settings are made so that the amount of data read in one prefetch access operation is large, prefetch
access can be started only after free space in the prefetch buffer for this amount is available. Thus, access to
the prefetch buffer is infrequent, and the external bus tends to be idle. For example, if the bus width is set to
16 bits and the burst length is set to "8", the amount of data read into the buffer in one prefetch operation is
16 bytes. Thus, a new prefetch access can be started only after the prefetch buffer is completely empty.
Adjust the optimum burst length to suit use and the environment after taking the above into consideration.
is set for the BST bits, the prefetch access always occurs in page mode/burst mode. Keep in
B
and xxxxxx0F , can be captured in the next prefetch access).
H H
, 4 bytes of
H
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