CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
[bits 7 and 6] ICP1 and ICP0
These bits are used as output compare interrupt flags. "1" is set to these bits when the compare register
value matches the 16-bit free-run timer value. While the interrupt request bits (ICE1 and ICE0) are
enabled, an output compare interrupt occurs when the ICP1 and ICP0 bits are set to "1". These bits are
cleared by writing "0". Writing "1" has no effect. "1" is always read by a read-modify-write instruction.
ICP1 or ICP0
ICP1: Corresponds to output compare 1.
ICP0: Corresponds to output compare 0.
If an external clock is specified for the free-running timer, a compare match and interrupt occur in the
next clock cycle. Therefore, when compare match output and an interrupt are generated, at least one
clock pulse must be inputted for the external clock specified for the free-running timer after the
comparison matching occurs.
[bits 5 and 4] ICE1 and ICE0
These bits are used as output compare interrupt enable bits. While the "1" is written to these bits, an
output compare interrupt occurs when an interrupt flag (ICP1 or ICP0) is set.
ICE1 or ICE0
ICE1: Corresponds to output compare 1.
ICE0: Corresponds to output compare 0.
[bits 3 and 2] Unused bits
"1" is always read from these bits.
[bits 1 and 0] CST1 and CST0
These bits are used to enable the match with 16-bit free-run timer. Ensure that a value is written to the
compare register and output control register before the compare operation is enabled.
CST1 or CST0
CST1: Corresponds to output compare 1.
CST0: Corresponds to output compare 0.
Since output compare is synchronized with the 16-bit free-running timer, stopping the 16-bit free-running
timer stops compare operation.
No output compare match (initial value)
Output compare match
Output compare interrupt disabled (initial value)
Output compare interrupt enabled
Compare operation disabled (initial value)
Compare operation enabled
Comparison with 16-bit free-running timer