CHAPTER 17 FLASH MEMORY
■ FR-CPU Programming Mode (16 Bits, Read/Write Enabled)
This mode enables data to be written and erased. As one word (32 bits) cannot be accessed in one cycle,
program execution in flash memory is disabled in this mode.
When specifying this mode, set the "WE" bit of the FLCR register to "1".
When a reset releases at CPU run time, the "WE" bit indicates "0". When setting this mode, set the
"WE" bit to "1". If the "WE" bit is set again to "0" through a writing operation or because of a reset,
the device enters ROM mode.
When the "RDY" bit of the FLCR register is "0", the "WE" bit cannot be rewritten. When rewriting
the "WE" bit, ensure that the "RDY" bit is set to "1".
One half-word (16 bits) can be read from the flash memory area in one cycle.
The automatic algorithm can be started by writing a command to flash memory. When the automatic
algorithm starts, data can be written to or erased from flash memory. For details on the automatic
algorithm, see Section "17.4 Automatic Algorithm of Flash Memory".
Address assignment and endians in this mode differ from those for writing with the ROM writer.
This mode inhibits reading data in words (32 bits).
The MB91F355A, MB91F353A, MB91F356B and MB91F357B each contain two 256K bytes/128K
bytes flash memories. Each flash memory (ROM 1 and ROM 2) must be controlled independently.
For details, see Section "17.4.1 Command Sequence".
■ Automatic Algorithm Execution Status
When the automatic algorithm is started in CPU programming mode, the operation status of the automatic
algorithm can be checked using the internal ready/busy signal (RDY/BUSYX). The level of this signal can
be read as the RDY bit in the FLCR register.
When the RDY bit is set to "0," data is being written or erased with the automatic algorithm, and no write
or erase command can be accepted. Moreover, data cannot be read from any address in flash memory.
Data read with the RDY bit set to "0" is a hardware sequence flag to indicate flash memory status.