CHAPTER 3 CPU AND CONTROL UNITS
A divide-by rate from the base clock can be set independently for each of the internal
operating clocks. With this function, an optimal operating frequency can be set for each
■ Setting the Divide-By Rate
Set a divide-by rate in basic clock division setting register 0 (DIVR0) and basic clock division setting
register 1 (DIVR1).
Each of these registers has four setting bits and (Register setting value + 1) is the divide-by rate of the clock
in relation to the base clock. Even if the divide-by rate setting is an odd number, the duty is always 50.
If the setting value is changed, the new divide-by rate becomes valid at the leading edge of the next clock
after the setting is made.
■ Initializing the Divide-By Rate
The divide-by rate setting is not initialized if an operation initialization reset (RST) occurs and the setting
made before the reset occurs is retained. The divide-by rate setting is initialized only if a settings
initialization reset (INIT) occurs. In the initial state, all clocks other than the peripheral clock (CLKP) have
a divide-by rate of 1. Thus, be sure to set the divide-by rate before changing the source clock to a faster
An upper-limit frequency for the operation is set for each clock. If you set a combination of source
clock, PLL multiply-by rate setting, and divide-by rate setting that results in a frequency exceeding
this upper-limit frequency, operation is not guaranteed. Be extra careful of the order in which you
change settings to select the source clock and to configure the associated setting items.