Fujitsu FR60 Hardware Manual page 53

■ Prefetch
When prefetch to an area set as little endian is allowed, restrict access to that area to word (32-bit) access.
Access will be incorrect if byte or halfword access is allowed.
■ Accessing I/O Ports
Only byte access is supported for port access.
■ Switching Shared Port Functions
Use the port function register (PFR) to switch the pins that also serve as ports. To switch the bus pins, use
the external bus setting.
■ Internal RAM
The function that restricts internal RAM size operates immediately after a reset is cleared. Only 4K bytes
can be used for data and another 4K bytes for program execution regardless of the amount of RAM
installed for the device.
To release the restriction function, rewrite the setting of the function.
In addition, if the above setting would be rewritten, include at least one NOP instruction immediately after
that processing.
■ Flash Memory
In programming mode, flash memory cannot be used for interrupt vector tables (reset is enabled).
■ Notes of PS Register
Since some instructions process the PS register first, interrupt processing routines can lead to breaks during
debugging or updating of the PS register flag due to the following exceptions.
Whichever the case, the program is designed to reprocess correctly after returning from EIT to ensure that
operation before and after EIT conforms to specifications.
1 The following operations may occur when (a) user interrupt/NMI is received, (b) step execution is
performed, (c) break occurs in a data event or emulator menu in an immediately preceding DIVOU/
DIVOS instruction.
(1) D0 and D1 flags precede and are renewed.
(2) EIT processing routine (user interruption, NMI or emulator) is executed.
(3) After returning from EIT, DIVOU/DIVOS instructions are executed and the D0 and D1 flags are
updated to the same value as (1).
2 When each ORCCR/STILM/MOV Ri and PS instruction is executed to permit interrupting with the user
interruption and the NMI factor generated, the following operations are done.
(1) The PS register precedes and is updated.
(2) EIT processing routine (user interruption, NMI, or emulator) is executed.
(3) After returning from EIT, the above instructions are executed and the PS register is updated to the
same value as (1).
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