Conversion Time Setting Register (Adct) - Fujitsu FR60 Hardware Manual

12.2.3

Conversion Time Setting Register (ADCT)

The conversion time setting register (ADCT) specifies the lengths of sampling period
and conversion periods a to c (see Figure 12.2-1 ). The width of each period is
calculated from "(value set in register × 2 + 1) × 0.04 µs" for a peripheral clock of 25
MHz.
The ADCT register must be accessed in 16-bit or 32-bit units.
Since the value of this register is undefined when it is reset, be sure to set data in the
ADCT register before starting the A/D converter.
■ Bit Configuration of the Conversion Time Setting Register (ADCT)
The bit configuration of the conversion time setting register (ADCT) is shown below.
Address : 00007A
Figure 12.2-1 shows the conversion time.
[Bits 15 to 12] SMP3 to SMP0 (sampling time)
The SMP3 to SMP0 bits specify the length of the sampling period.
[Bits 11 to 8] CV03 to CV00 (convert time a)
The CV03 to CV00 bits specify the length of the conversion period a.
[Bits 7 to 4] CV13 to CV10 (convert time b)
The CV13 to CV10 bits specify the length of the conversion period b.
[Bits 3 to 0] CV23 to CV20 (convert time c)
The CV23 to CV20 bits specify the length of the conversion period c.
bit 7 6 5
CV13 CV12 CV11
H
X X X
R/W R/W R/W
bit 15 14 13
SMP3 SMP2 SMP1 SMP0
X X X
R/W R/W R/W
Figure 12.2-1 Conversion Time
Sampling period Conversion
period a
Start of A/D conversion
4 3 2
CV10 CV23 CV22 CV21
X X X X
R/W R/W R/W R/W
12 11 10
CV03 CV02 CV01
X X X X
R/W R/W R/W R/W
Conversion
Conversion
period b period c
End of conversion
(generation of
interrupt)
1 0
CV20
<− Initial value
X
<− Bit attribute
R/W
9 8
CV00
<− Initial value
X
<− Bit attribute
R/W
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