Fujitsu FR60 Hardware Manual page 150

CHAPTER 3 CPU AND CONTROL UNITS
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Main Clock Oscillation Stabilization Wait Timer (When Subclock Selected)
The main clock oscillation stabilization wait timer is a 26-bit timer that counts up in synchronization with
the main clock. The operation of this timer is not affected by clock source selection or the clock division.
The main clock oscillation stabilization wait timer is used to measure the main clock oscillation
stabilization wait time during subclock is operating.
Main clock oscillation can be controlled by Bit 0 (OSCDS1 bit) of the oscillation control register (OSCCR)
while the device is operating on the subclock. This timer is used to measure the oscillation stabilization
wait time when main clock oscillation is restarted after it has been stopped.
Follow the procedure below for switching the clock source to the main clock when the device is operating
on the subclock with the main clock stopped.
1. Clear the main clock oscillation stabilization wait timer.
2. Set Bit 0 (OSCDS1 bit) of the oscillation control register (OSCCR) to "0" to start main clock
oscillation.
3. Use the main clock oscillation stabilization wait timer to wait until the main clock oscillation is
stabilized.
4. After the main clock has been stabilized, use Bits 9 and 8 (CLKS1 and CLKS0 bits) of the clock source
register (CLKR) to switch the clock source from the subclock to main clock.
Note:
If the clock source is switched to the main clock before the main clock is stabilized, an unstable clock
is supplied and subsequent operation is unpredictable. Be sure to switch to the main clock after the
main clock has been stabilized.
For more information on the main clock oscillation stabilization wait timer, see Section "3.13 Main
Clock Oscillation Stabilization Wait Timer".
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Peripheral Stop Control
Peripheral stop control is used to control the clock supply to peripheral resources.
Power saving can be implemented by stopping the clock supply to peripheral resources not being used.
For details, see Section "3.14 Peripheral Stop Control".
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