Operations - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.7.8

Operations

This section describes the operation of FR family microcontrollers.
In the following, it is assumed that the transfer source PC indicates the address of the
instruction that detected an EIT cause. In addition, "address of the next instruction"
means that the instruction that detected EIT is as follows:
• If LDI is 32: PC + 6
• If LDI is 20 and COPOP, COPLD, COPST, and COPSV are used: PC + 4
• Other instructions: PC + 2
■ Operation of User Interrupt/NMI
If an interrupt request for a user interrupt or a user NMI occurs, whether the request can be accepted is
determined with the following procedure:
[Determining whether an interrupt request can be accepted]
1. Compare the interrupt levels of requests that have occurred simultaneously and select the request with
the highest level (the smallest value). As levels to be compared, the value held in the corresponding ICR
is used for a maskable interrupt and a predetermined constant is used for an NMI.
2. If multiple interrupt requests with the same level occur, select the interrupt request with the smallest
interrupt number.
3. Mask and do no accept an interrupt request with an interrupt level greater than or equal to the level
mask value. Go to Step 4) if the interrupt level is less than the level mask value.
4. Mask and do not accept the selected interrupt request if it is maskable and the I flag is set to 0. Go to
Step 5) if the I flag is "1". If the selected interrupt request is an NMI, go to Step 5) regardless of the I
flag value.
5. If the above conditions are met, the interrupt request is accepted at a break in the instruction processing.
If a user interrupt or NMI request is accepted when EIT requests are detected, the CPU operates as follows,
using an interrupt number corresponding to the accepted interrupt request.
Note: The parentheses in [Operation] indicate an address pointed to by the register.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. Address of next instruction → (SSP)
5. Interrupt level of accepted request → ILM
6. "0" → S flag
7. (TBR + Vector offset of accepted interrupt request) → PC
After the interrupt sequence was finished, the CPU performs the detection of new EIT before processing
the lead instruction of the handler. If an acceptable EIT is detected at this time, the CPU enters the EIT
process sequence.
Executing the ORCCR,STILM and MOV Ri,PS command to allow interruptions when user interruption or
NMI factors have been occurred may executes above commands twice before and after the interrupt
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