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INDEX
External Bus Access
External Bus Access ......................................... 193
External Bus Clock
External Bus Clock (CLKT) .............................. 109
External Bus Interface
Block Diagram of the External Bus Interface ...... 164
Features of the External Bus Interface ................ 162
Procedure for Setting the External Bus
Interface ............................................. 230
Register Overview of External Bus Interface....... 167
External Bus Interface Register
List of External Bus Interface Registers.............. 166
External Clock
Note on Using an External Clock ......................... 32
External Device
Example of Connection with External Devices
.......................................................... 196
External Hold
DMA Transfer Request During External Hold
.......................................................... 507
External Hold Request
External Hold Request During DMA Transfer
.......................................................... 507
Simultaneous Occurrence of a DMA Transfer Request
and an External Hold Request............... 507
External I/O and External Memory
Transfer Between External I/O and External
Memory ............................................. 521
External Input Pin
External Input Pin Corresponding to Each Input
Capture Channel.................................. 426
External Interrupt
Block Diagram of the External Interrupt and
NMI Controller ................................... 343
Details of the Registers for the External Interrupt and
NMI Controller ................................... 344
External Interrupt and NMI Controller
Registers ............................................ 342
External Interrupt Request Level........................ 349
Operating Procedure for an External Interrupt
.......................................................... 348
Operation of an External Interrupt...................... 348
External Interrupt Request Level
External Interrupt Request Level........................ 349
External Interrupt Request Register
Bit Configuration of the External Interrupt Request
Register (EIRRn)................................. 346
External Level Register
Bit Configuration of External Level Register (ELVRn)
.......................................................... 347
External Pin Transfer Request
If an External Pin Transfer Request is Reentered
During Transfer................................... 521
628
External Transfer Request Pin
External Transfer Request Pin ........................... 496
External Wait
With External Wait
(TYP[3:0]=0101
Without External Wait
(TYP[3:0]=0100
......................................................... 215
External Wait Timing
External Wait Timing
(TYP[3:0]=0001
External-ROM
Bus Mode 2 (External-ROM/External-bus Mode)
........................................................... 91
F
F-Bus RAM Limit Control Register
FRLR: Instruction RAM Limit Control Register
(F-Bus RAM Limit Control Register)
......................................................... 578
Feature
Features .......................................................... 387
Features of EIT .................................................. 72
2
Features of I
C Interface................................... 440
Features of the 8-bit D/A Converter ................... 380
Features of the A/D Converter........................... 364
Features of the External Bus Interface................ 162
Features of the Internal Architecture .................... 50
Features of the Output Compare Module ............ 432
Flash Control/Status Register
Configuration of the Flash Control/Status Register
(FLCR) (CPU Mode) .......................... 540
Flash Memory
Block Diagram of Flash Memory ...................... 535
Configuration of the Flash Memory Wait Register
(FLWC) ............................................. 543
Erasing Data (Chip Erase) From Flash Memory
......................................................... 561
Flash Memory ................................................... 35
Flash Memory Access Modes............................ 545
Memory Map of Flash Memory......................... 535
Outline of Flash Memory.................................. 534
Overview of Flash Memory Registers ................ 539
Overview of Flash Memory Write/Erase ............ 557
Overview of the Flash Memory Automatic
Algorithm .......................................... 547
Reading/Resetting Flash Memory ...................... 558
Restarting Sector Erase in Flash Memory ........... 565
Sector Address Table of Flash Memory.............. 537
Temporarily Stopping Sector Erase in Flash
Memory ............................................. 564
Writing Data to Flash Memory.......................... 559
Flash Memory Register
Overview of Flash Memory Registers ................ 539
,AWR=1008
).......... 216
B
H
and AWR=0008
)
B
H
).......... 209
,AWR=2008
B
H

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