Fujitsu FR60 Hardware Manual page 434

CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE
Notes:
• Be sure to specify the transfer direction before writing data to the serial shift data register (SDR).
• The BDS bit is cleared to "0" by a reset. This bit can be read and written
[Bits 7 to 4, 1, and 0]: Unused bits
These bits are not used.
■ Serial Shift Data Register (SDR)
The bit configuration of the serial shift data register (SDR) is shown below.
This register must be accessed in byte units.
SDR
Address : 000027
00002B
00002F
The serial shift data register is a serial data register that holds the serial I/O data to be transferred. During
operation, data must not be written to or read from the SDR.
Note:
The MB91F353A/351A/352A/353A do not have SIO ch5. (Setting of 000027
■ SIO Test Register (SES)
The bit configuration of the SIO test register (SES) is shown below.
This register must be accessed in byte units.
SES
Address : 000026
00002A
00002E
[Bits 9 and 8] TST1 and TST0
The TST1 and TST0 bits are used for testing. Always write "0" to these bits.
Note:
The MB91F353A/351A/352A/353A do not have SIO ch5. (Setting of 000026
invalid.)
416
7 6 5
D7 D6 D5
H
R/W R/W R/W
H
H
15 14 13
- - -
H
H
H
4 3 2
D4 D3 D2 D1
R/W R/W R/W R/W
12 11 10
- - - TST1
R/W
1 0
D0 Initial value: XX
R/W
(undefined)
in the SDR is invalid.)
H
9 8
TST0 Initial value: ------00
R/W
(undefined)
in the SES register is
H
H
B