Fujitsu FR60 Hardware Manual page 136

CHAPTER 3 CPU AND CONTROL UNITS
[Bits 13 to 11] TBC2, TBC1, TBC0 (TimeBasetimer Counting time select)
These bits set the interval time of the timebase counter that is used for the timebase timer.
The values written to these bits determine the interval time, which can be selected from the eight types
listed in the table below:
TBC2 TBC1 TBC0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
φ: Frequency of the system base clock
• The initial value is undefined. Be sure to set a value before enabling an interrupt.
• These bits are readable and writable.
[Bit 10] (reserved bit)
This bit is reserved. The read value is undefined. Writing to this bit has no effect on operation.
[Bit 9] SYNCR (SYNChronous Reset enable)
This bit is the synchronous reset enable bit.
This bit specifies whether normal reset operation or synchronous reset operation is executed when an
operation initialization reset (RST) request occurs. Normal reset operation performs a reset (RST)
immediately. Synchronous reset operation performs an operation initialization reset (RST) after all bus
access has stopped.
Value
0
1
• This bit is initialized to "0" by a reset (INIT).
• This bit is readable and writable.
118
Timer interval
time
0 φ x 2 11
1 φ x 2 12
0 φ x 2 13
1 φ x 2 22
0 φ x 2 23
1 φ x 2 24
0 φ x 2 25
1 φ x 2 26
Normal reset operation (initial value)
Synchronous reset operation
If the source oscillation is 12.5 MHz
and PLL is multiplied by 4
41.0 [µs]
81.9 [µs]
164 [µs]
83.9 [ms]
168 [ms]
336 [ms]
672 [ms]
1342 [ms]
Explanation
If the subclock is
32 kHz
61.4 [ms]
123 [ms]
246 [ms]
126 [s]
256 [s]
512 [s]
1024 [s]
2048 [s]