Fujitsu FR60 Hardware Manual page 169

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[Bit 14] WIE (timer interrupt enable)

This bit enables or disables the interrupt request output to the CPU. If this bit and main clock oscillation

stabilization interrupt request flag bit are "1", a main clock oscillation stabilization wait timer interrupt

request is outputted.

Output of main clock oscillation stabilization wait timer interrupt request disabled

(default value)

Output of main clock oscillation stabilization wait timer interrupt request enabled

This bit is cleared to "0" by a reset (INIT) request.

Data can be written to and read from this bit.

[Bit 13] WEN (timer enable)

This bit enables timer operation.

When this bit is "1", the timer counts.

The timer is stopped (default value).

The timer operates.

This bit is cleared to "0" by a reset (INIT) request.

Data can be written to and read from this bit.

[Bits 12, 11] (reserved bits)

These bits are reserved. When writing data to these bits, be sure to write "0". (Writing "1" to these bits

is not allowed).

Data read from these bits is undefined.

[Bits 10, 9] WS1, WS0 (timer interval select 1, 0)

These bits select the interval of the interval timer.

One of the following three intervals is selected according to the output bits of the main clock oscillation

stabilization wait timer counter:

These bits are cleared to "00" by a reset (INIT) request.

Data can be written to and read from these bits.

To use the main clock oscillation stabilization wait timer, write data to this register.

Interval timer interval (at F

Setting prohibited (default value)

Mb91350a series