■ Wait Time after Returning from Stop Mode
If, after a program starts execution, the device enters stop mode and then stop mode is cleared, the
oscillation stabilization wait time specified in the program is internally generated.
If the clock oscillation circuit selected as the source clock is set to stop in stop mode, the oscillation
stabilization wait time of the oscillation circuit or the lock wait time of the PLL in use, whichever is longer,
is required. Set the oscillation stabilization wait time before entering stop mode.
If the clock oscillation circuit selected as the source clock is not set to stop in stop mode, the PLL does not
automatically stop. No oscillation stabilization wait time is required unless the PLL has stopped. Setting the
oscillation stabilization wait time to the minimum value before stop mode is entered is recommended.
■ Wait Time after Switching From the Subclock to the Main Clock
If the PLL is used after switching from the subclock to the main clock, the PLL output must not be used
until the lock wait time has elapsed. This applies regardless of the value for bit 2 (PLL1EN) of the CLKR
(clock source register).
Even if there is a lock wait time, the program can be executed if the source clock has been selected to use a
Fujitsu recommends using a timebase timer interrupt for the PLL lock wait time in this case.