Uart Registers - Fujitsu FR60 Hardware Manual

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CHAPTER 14 UART, SERIAL I/O INTERFACE (SIO), INPUT CAPTURE MODULE, AND OUTPUT COMPARE

UART Registers

This section describes the configuration and functions of the registers used by the

■ Serial Mode Register (SMR)

The bit configuration of the serial mode register (SMR) is shown below.

Note: The MB91F353A/351A/352A/353A do not have SMR ch4.

Address : ch0 000063

The SMR specifies the UART operating mode. Set the operating mode while operation is stopped. Do not

write to this register during operation.

[Bits 7, 6] MD1, MD0 (MoDe select)

These bits are used to select a UART operating mode. Table 14.1-1 lists the UART operating modes

that can be selected.

Table 14.1-1 Selecting UART Operating Modes

In Mode 1, which is CLK asynchronous mode (multiprocessor), more than one slave CPU can be

connected to one host CPU. Since this resource cannot identify the data format of received data,

however, only the master in multiprocessor mode is supported.

Because the parity check function cannot be used, set PEN of the SCR register to "0".

[Bits 5, 4] (reserved)

Always write "1" to these bits.

Operating mode

Asynchronous (start-stop synchronization) normal mode

[initial value]

Asynchronous (start-stop synchronization) multiprocessor

CLK synchronous mode

Setting disabled

Initial value

Mb91350a series