Fujitsu FR60 Hardware Manual page 230

CHAPTER 4 EXTERNAL BUS INTERFACE
■ Setting of CS → RD/WR Setup and of RD/WR → CS Hold
(TYP[3:0]=0000
B
Figure 4.5-8 shows setting of the CS → RD/WR setup and setting of RD/WR → CS hold.
Figure 4.5-8 Setting of CS → RD/WR Setup and RD/WR → CS Hold
READ
WRITE
Setting "1" for the W01 bit of the AWR register enables the CS → RD/WR setup delay to be set. Set
•
this bit to extend the period between chip select assertion and read/write strobe.
Setting "1" for the W00 bit of the AWR register enables the RD/WR → CS hold delay to be set. Set this
•
bit to extend the period between read/write strobe negation and chip select negation.
The CS → RD/WR setup delay (W01 bit) and RD/WR → CS hold delay (W00 bit) can be set
•
independently.
• When making successive accesses within the same chip select area without negating the chip select,
neither a CS → RD/WR setup delay nor an RD/WR → CS hold delay is inserted.
• If a setup cycle for determining the address or a hold cycle for determining the address is needed, set
"1" for the address → CS delay setting (W02 bit of the AWR register).
212
,AWR=000B )
H
MCLK
A[23:0]
AS
CSn
RD
D[31:16]
WRn
D[31:16]
CS->RD/WR
RD/WR->CS
Delay Delay