Fujitsu FR60 Hardware Manual page 626

APPENDIX
Table D-7 Shift
Mnemonic
LSL Rj, Ri
*LSL #u5, Ri (u5:0 to 31)
LSL #u4, Ri
LSL2 #u4, Ri
LSR Rj, Ri
*LSR #u5, Ri (u5:0 to 31)
LSR #u4, Ri
LSR2 #u4, Ri
ASR Rj, Ri
*ASR #u5, Ri (u5:0 to 31)
ASR #u4, Ri
ASR2 #u4, Ri
Table D-8 Immediate Value Set/16-Bit/32-Bit Immediate Value Transfer
Mnemonic
LDI:32 #i32, Ri
LDI:20 #i20, Ri
LDI:8 #i8, Ri
*
*LDI # {i8 | i20 | i32} ,Ri
* : If the immediate data is represented as absolute values, the assembler selects automatically from i8, i20, and i32.
If immediate data contains a relative value or external reference symbol, i32 is selected.
Table D-9 Memory Load
Mnemonic
LD @Rj, Ri
LD @(R13,Rj), Ri
LD @(R14,disp10), Ri
LD @(R15,udisp6), Ri
LD @R15+, Ri
LD @R15+, Rs
LD @R15+, PS
LDUH @Rj, Ri
LDUH @(R13,Rj), Ri
LDUH @(R14,disp9), Ri
LDUB @Rj, Ri
LDUB @(R13,Rj), Ri
LDUB @(R14,disp8), Ri
* : In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below:
disp10/4 → o8, disp9/2 → o8, disp8 → o8; disp10, disp9, and disp8 have a sign.
udisp6/4 → o4; udisp6 has no sign.
608
Type OP CYCLE
A B6
C' B4
C B4
C B5
A B2
C' B0
C B0
C B1
A BA
C' B8
C B8
C B9
Type OP CYCLE
E 9F-8
C 9B
B C0
Type OP CYCLE
A 04 b
A 00 b
B 20 b
C 03 b
E 07-0 b
E 07-8 b
E 07-9 1+a+b
A 05 b
A 01 b
B 40 b
A 06 b
A 02 b
B 6 b
NZVC
1 CC-C
Ri << Rj
1 CC-C
Ri << u5
1 CC-C
Ri << u4
1 CC-C
Ri <<(u4+16)
1 CC-C
Ri >> Rj
1 CC-C
Ri >> u5
1 CC-C
Ri >> u4
1 CC-C
Ri >>(u4+16)
1 CC-C
Ri >> Rj
1 CC-C
Ri >> u5
1 CC-C
Ri >> u4
1 CC-C
Ri >>(u4+16)
NZVC
→
3 ----
i32 Ri
→
2 ----
i20 Ri
→
1 ----
i8 Ri
{i8 | i20 | i32}
NZVC Operation
→
----
(Rj) Ri
→
----
(R13+Rj)
----
(R14+disp10)
----
(R15+udisp6)
→
----
(R15) Ri,R15+=4
→
----
(R15) Rs, R15+=4
→
CCCC
(R15) PS, R15+=4
→
----
(Rj) Ri
→
----
(R13+Rj) Ri
→
----
(R14+disp9)
→
----
(Rj) Ri
→
----
(R13+Rj) Ri
→
----
(R14+disp8)
Operation
→
Logical shift
Ri
→
Ri
→
Ri
→
Ri
→
Logical shift
Ri
→
Ri
→
Ri
→
Ri
→
Arithmetic shift
Ri
→
Ri
→
Ri
→
Ri
Operation Remarks
High-order 12 bits are
zero-extended.
High-order 24 bits are
zero-extended.
→
Ri
Remarks
Ri
→
Ri
→
Ri
Rs: Special register
Zero extension
Zero extension
Zero extension
Ri
Zero extension
Zero extension
Zero extension
Ri
Remarks
*