Fujitsu FR60 Hardware Manual page 638

INDEX
Index
Numerics
0 Detection
0 Detection ...................................................... 360
0 Detection Data Register (BSD0) ..................... 358
0 Detection Data Register
0 Detection Data Register (BSD0) ..................... 358
1 Detection
1 Detection ...................................................... 360
1 Detection Data Register (BSD1) ..................... 358
1 Detection Data Register
1 Detection Data Register (BSD1) ..................... 358
10-bit Slave Address Mask Register
10-bit Slave Address Mask Register (ITMK) ...... 458
10-bit Slave Address Register
10-bit Slave Address Register (ITBA) ................ 457
16-bit
32-bit/16-bit Bus Converter................................. 52
16-bit Free-running Timer
Block Diagram of the 16-bit Free-running
Timer ................................................. 279
Clearing of the Counter for the 16-bit Free-running
Timer ................................................. 284
Overview of the 16-bit Free-running Timer......... 278
Timing of 16-bit Free-running Timer Counting
.......................................................... 285
Timing of Clearing of the 16-bit Free-running
Timer ................................................. 285
16-bit Free-running Timer Register
16-bit Free-running Timer Registers................... 279
16-bit Input Capture
16-bit Input Capture Operation .......................... 430
Input Timing for 16-bit Input Capture ................ 430
16-bit Output Compare
Operation of the 16-bit Output Compare
Module............................................... 437
Timing of 16-bit Output Compare Operation....... 438
16-bit Reload Register
16-bit Reload Register (TMRLR)....................... 291
16-bit Reload Timer
Block Diagram of the 16-bit Reload Timer ......... 288
Overview of the 16-bit Reload Timer ................. 286
620
16-bit Reload Timer Register
16-bit Reload Timer Registers........................... 287
16-bit Timer Register
16-bit Timer Register (TMR) ............................ 291
2-Cycle Transfer
2-Cycle Transfer (External -> I/O)
(TYP[3:0] = 0000
) ..................................... 226
IOWR = 00
H
2-Cycle Transfer (I/O -> External)
(TYP[3:0] = 0000
) ..................................... 227
IOWR = 00
H
2-Cycle Transfer
(The Timing is the Same for Internal RAM
-> External I/O and RAM and for External
I/O and RAM -> Internal RAM.)
(TYP[3:0] = 0000
) ..................................... 225
IOWR = 00
H
Flow of Data During 2-Cycle Transfer ............... 525
Step/Block Transfer 2-Cycle Transfer ................ 499
Step/Block Transfer 2-Cycle Transfer Fly-by
Transfer ............................................. 500
32-bit
32-bit/16-bit Bus Converter ................................ 52
7-bit Slave Address Mask Register
7-bit Slave Address Mask Register (ISMK) ........ 461
7-bit Slave Address Register
7-bit Slave Address Register (ISBA).................. 460
8/16-bit Up/Down Counter
Block Diagram of the 8/16-bit Up/Down
Counters/Timers (ch0)......................... 250
Block Diagram of the 8/16-bit Up/Down
Counters/Timers (ch1)......................... 251
Characteristics of the 8/16-bit Up/Down
Counters/Timers ................................. 247
List of Registers of the 8/16-bit Up/Down
Counters/Timers ................................. 248
Overview of the 8/16-bit Up/Down
Counters/Timers ................................. 246
8-bit D/A Converter
8-bit D/A Converter Registers ........................... 380
Block Diagram of the 8-bit D/A Converter ......... 381
Features of the 8-bit D/A Converter ................... 380
, AWR = 0008 , and
B H
, AWR = 0008 , and
B H
, AWR = 0008 , and
B H