Fujitsu FR60 Hardware Manual page 164

CHAPTER 3 CPU AND CONTROL UNITS
■ Watch Timer Interrupt
If the set interval time elapses while the watch timer counter is counting with the subclock, the watch timer
interrupt flag (WIF) is set to "1". Then, if the watch timer interrupt enable bit (WIE) has been set to "1"
(interrupt output enabled), an interrupt request is outputted to the CPU.
If subclock oscillation has stopped (see "■ Operation of Interval Timer Function" in Section "3.13 Main
Clock Oscillation Stabilization Wait Timer"), a watch interrupt will not occur because counting has also
stopped.
To clear an interrupt request, write "0" to the WIF bit using the interrupt processing routine. Note that the
WIF bit is set at the trailing edge of the selected frequency-divide output regardless of the value of the WIE
bit.
Notes:
• The WIF and WCL bits must be cleared to "0" (WIF=WCL=0) at the same time if watch timer
interrupt request output is to be enabled (WIE = 1) or the value of the WS1 and WS0 bits are to
be changed after release from the reset state.
• If the WIE bit is changed from "0" to "1" to enable interrupt output when the WIF bit is "1", an
interrupt request is output immediately.
• If a counter clear (WCL bit of WPCR is "1") and overflow of selected bits occur at the same time,
the WIF bit is not set to "1".
■ Operation of Interval Timer Function
The watch timer counter continues incremental counting while the subclock is running. When subclock
oscillation stops, counting stops in the following cases:
• Counting is stopped throughout stop mode if the MB91350A is put into stop mode by stopping subclock
oscillation with Bit 1 [OSCD2 bit] of the standby control register [STCR] set to "1".
• To make the watch timer operate in stop mode, set the OSCD2 bit to "0" before entry to the standby
state, because the OSCD2 bit is initialized to "1" at reset by an INIT request.
If the counter is cleared (WCL bit is cleared to "0"), the counter starts counting from 0000
count reaches 7FFF
divide output selected for the interval timer is detected during incremental counting, the watch interrupt
request (WIF) bit is set to "1". In other words, a watch timer interrupt request is generated at the selected
intervals on the basis of the selected interval time.
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, the counter restarts counting from 0000
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. When the trailing edge of the frequency-
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. When the
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