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Overview
Many Xilinx video processing cores utilize the AXI-4 Stream video protocol to transfer video
between cores. Between systems, video is commonly transmitted with explicit blanking and
sync signals for horizontal and vertical timing, and a data valid signal. DVI is an example of
such a transmission mode. The Video In to AXI4-Stream core converts incoming video with
explicit sync and timing to the AXI4-Stream Video protocol in order to interface to Xilinx
video processing cores that use this protocol.
The Video In to AXI-4 Stream core accepts video inputs. For the purposes of this document,
video is defined as parallel video data along with a pixel clock and one of the following sets
of timing signals:
•
Vsync, Hsync, and DE
•
Vblank, Hblank, and DE
•
Vsync, Hsync, Vbank, Hblank, and DE
Any of these sets of signals is sufficient for the operation of the Video In to AXI4-Stream
core. The particular choice is important to the VTC detector, so the generation of the VTC
core should specify which set of timing signals will be used. The output side of the core is
an AXI4-Stream interface in master mode. This interface consists of parallel video data,
tdata, handshaking signals tvalid and tready, and two flags, tlast and tuser which
serve to identify certain pixels in the video stream. The flag tlast designates the last valid
pixel of each line, and is also known as the end of line (EOL). The flag tuser designates the
first valid pixel of a frame, and is known as start of frame (SOF). These two flags are
necessary to identify pixel locations on the AXI4 stream bus because there are no sync or
blank signals. Only active pixel are carried on the bus. The Video IP: AXI Feature Adoption
section of the
UG761 AXI Reference Guide
protocol in detail.
Video In to AXI4-Stream
PG043 April 24, 2012
describes the video over AXI4 Stream Video
www.xilinx.com
Chapter 1
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