ARM CoreLink GIC-600AE Controller Manuals

Manuals and User Guides for ARM CoreLink GIC-600AE Controller. We have 1 ARM CoreLink GIC-600AE Controller manual available for free PDF download: Technical Reference Manual

ARM CoreLink GIC-600AE Technical Reference Manual (268 pages)

Generic Interrupt Controller

Brand: ARM | Category: Controller | Size: 2.62 MB

Table of Contents
5
Introduction
12
Product Revision Status
12
Intended Audience
12
Conventions
12
Useful Resources
14
About the GIC-600AE
16
Components
16
Compliance
20
Features
21
Test Features
22
Product Documentation
22
Product Revisions
23
Components and Configuration
25
Distributor
25
Distributor AXI4-Stream Interfaces
26
Distributor ACE-Lite Subordinate Interface
27
Distributor ACE-Lite Manager Interface
28
Distributor Q-Channels
29
Distributor P-Channel
30
Distributor Configuration
30
Redistributor
31
Redistributor AXI4-Stream Interface
32
Redistributor GIC Stream Protocol Interface
32
Redistributor Q-Channel
32
Redistributor PPI Signals
33
Redistributor Configuration
33
Interrupt Translation Service
34
ITS ACE-Lite Subordinate Interface
36
ITS ACE-Lite Manager Interface
37
ITS AXI4-Stream Interface
38
ITS Q-Channel
39
ITS Configuration
39
Encapsulator
40
ACE-Lite Interfaces
40
Encapsulator Configuration
41
SPI Collator
42
SPI Collator AXI4-Stream Interface
42
SPI Collator Wires
42
SPI Collator Power Q-Channel
43
SPI Collator Clock Q-Channel
43
SPI Collator Configuration
44
Wake Request
44
Wake Request AXI4-Stream Interface
45
Wake Request Configuration
45
Interconnect
45
Interconnect Configuration
46
Hierarchy
46
Operation
48
Interrupt Types
48
Sgis
48
Ppis
48
Spis
49
Lpis
49
Choosing between Lpis and Spis
50
Interrupt Groups and Security
51
Physical Interrupt Signals (Ppis and Spis)
52
Affinity Routing and Assignment
53
SPI Routing and 1 of N Selection
54
Power Management
56
Redistributor Power Management
56
Processor Core Power Management
57
Other Power Management
58
Getting Started
60
Backwards Compatibility
60
Its
60
ITS Cache Control, Locking, and Test
61
ITS Commands and Errors
62
LPI Caching
63
Memory Access and Attributes
64
Msi-64
65
Rams and ECC
66
Performance Monitoring Unit
67
Reliability, Accessibility, and Serviceability
68
Non-Secure Access
69
Scrub
69
Error Record Classification
69
ECC Error Reporting and Recovery
69
Error Recovery and Fault Handling Interrupts
70
Error Handling Records
71
Bus Errors
87
Multichip Operation
88
Connecting the Chips
89
Changing the Routing Table Owner
90
SPI Ownership for Multichip Operation
91
Power Control and P-Channel
91
Isolating a Chip from the System
92
SPI Operation for Multichip Operation
93
LPI Multichip Operation
94
Programmers Model
95
Register Map
95
Discovery
97
GIC-600AE Register Access and Banking
98
Distributor Registers (GICD/GICDA) Summary
98
GICD_CTLR, Distributor Control Register
101
GICD_TYPER, Interrupt Controller Type Register
102
GICD_IIDR, Distributor Implementer Identification Register
103
GICD_FCTLR, Function Control Register
104
GICD_SAC, Secure Access Control Register
106
GICD_CHIPSR, Chip Status Register
107
GICD_DCHIPR, Default Chip Register
109
Gicd_Chipr<N>, Chip Registers
109
Gicd_Iclarn, Interrupt Class Registers
111
Gicd_Icerrrn, Interrupt Clear Error Registers
112
GICD_CFGID, Configuration ID Register
112
GICD_PIDR4, Peripheral ID4 Register
114
GICD_PIDR3, Peripheral ID3 Register
114
GICD_PIDR2, Peripheral ID2 Register
115
GICD_PIDR1, Peripheral ID1 Register
116
GICD_PIDR0, Peripheral ID0 Register
117
Distributor Registers (GICM) for Message-Based Spis Summary
118
GICM_TYPER, Message-Based Type Register
119
GICM_IIDR, Message-Based Distributor Implementer Identification Register
120
Redistributor Registers for Control and Physical Lpis Summary
121
GICR_IIDR, Redistributor Implementation Identification Register
123
GICR_TYPER, Redistributor Type Register
124
GICR_WAKER, Power Management Control Register
125
GICR_FCTLR, Function Control Register
126
GICR_PWRR, Power Register
127
GICR_CLASSR, Class Register
129
GICR_PIDR2, Peripheral ID2 Register
129
Redistributor Registers for Sgis and Ppis Summary
130
GICR_MISCSTATUSR, Miscellaneous Status Register
132
GICR_IERRVR, Interrupt Error Valid Register
133
GICR_SGIDR, SGI Default Register
134
GICR_CFGID0, Configuration ID0 Register
135
GICR_CFGID1, Configuration ID1 Register
136
ITS Control Register Summary
137
GITS_IIDR, ITS Implementer Identification Register
138
GITS_TYPER, ITS Type Register
139
GITS_FCTLR, Function Control Register
140
GITS_OPR, Operations Register
143
GITS_OPSR, Operation Status Register
144
GITS_CFGID, Configuration ID Register
145
GITS_PIDR2, Peripheral ID2 Register
146
ITS Translation Register Summary
147
GICT Register Summary
148
Gict_Err<N>Fr, Error Record Feature Register
149
Gict_Err<N>Ctlr, Error Record Control Register
150
Gict_Err<N>Status, Error Record Primary Status Register
151
Gict_Err<N>Addr, Error Record Address Register
152
Gict_Err<N>Misc0, Error Record Miscellaneous Register 0
153
Gict_Err<N>Misc1, Error Record Miscellaneous Register 1
158
GICT_ERRGSR, Error Group Status Register
159
Gict_Errirqcr<N>, Error Interrupt Configuration Registers
160
GICT_DEVID, Device Configuration Register
161
GICT_PIDR2, Peripheral ID2 Register
162
GICP Register Summary
163
Gicp_Evcntrn, Event Counter Registers
164
Gicp_Evtypern, Event Type Configuration Registers
164
Gicp_Svrn, Shadow Value Registers
168
Gicp_Frn, Filter Registers
169
GICP_CNTENSET0, Counter Enable Set Register 0
170
GICP_CNTENCLR0, Counter Enable Clear Register 0
170
GICP_INTENSET0, Interrupt Contribution Enable Set Register 0
171
GICP_INTENCLR0, Interrupt Contribution Enable Clear Register 0
172
GICP_OVSCLR0, Overflow Status Clear Register 0
173
GICP_OVSSET0, Overflow Status Set Register 0
174
GICP_CAPR, Counter Shadow Value Capture Register
175
GICP_CFGR, Configuration Information Register
176
GICP_CR, Control Register
176
GICP_IRQCR, Interrupt Configuration Register
177
GICP_PIDR2, Peripheral ID2 Register
178
FMU Register Summary
179
Fmu_Err<N>Fr, Error Record Feature Register
180
Fmu_Err<N>Ctlr, Error Record Control Register
181
Fmu_Err<N>Status, Error Record Primary Status Register
182
FMU_ERRGSR, Error Group Status Register
184
FMU_KEY, FMU Key Register
184
FMU_PINGCTLR, Ping Control Register
185
FMU_PINGNOW, Ping Now Register
186
FMU_SMEN, Safety Mechanism Enable Register
187
FMU_SMINJERR, Safety Mechanism Inject Error Register
189
FMU_PINGMASK, Ping Mask Register
190
FMU_STATUS, FMU Status Register
191
FMU_ERRIDR, Error Record ID Register
191
Functional Safety
193
Safety Mechanism Overview
193
Fault Management Unit
196
FMU APB4 Interface
197
Error Signaling
197
Error Record Format
198
FMU Reset
199
Safety Mechanism Ids
199
Ping Mechanisms
203
Lock and Key Mechanism
206
Correctable Error Enable
207
Software Interaction
207
Fusa Programmer's View
209
Fusa I/O
209
Non-Architected Fusa Ports
209
P-Channel and Q-Channel Fusa Ports
210
AMBA Interface Fusa Ports
211
Clocks and Resets
211
Clocks
212
Resets
214
Lock-Step Protection
217
Comparators
218
Non-Resettable Flops
219
Reset
219
Error Injection
219
RAM Protection
219
SECDED ECC Data Protection
220
Address Protection
220
RAM Scrubbing
221
External Interface Protection
221
ACE-Lite Interface Parity Protection
222
AXI4-Stream Interface Parity Protection
224
APB Interface Parity Protection
225
AXI4-Stream Internal Interconnect Protection
226
GIC-Rendered Partially Duplicated Interconnect
226
Non-GIC Interconnect IP
228
P-Channel and Q-Channel Protection
232
CHK Bit Timing
235
Transient Faults
236
Stuck-At Faults
238
Disabling P-Channel and Q-Channel Safety Mechanisms
239
P-Channel
239
Q-Channel
241
PPI and SPI Interrupt Interface Protection
244
PPI and SPI CHK Bit Timing
244
PPI and SPI Transient Faults
245
PPI and SPI Stuck-At Faults
246
PPI and SPI Configuration Parameters
246
Systematic Fault Watchdog Protection
246
DFT Protection
247
Mbist
247
Atpg/Scan
248
Lbist
248
Generic Fault Inputs
248
Configuration and Parameters
249
Signal Descriptions
250
Common Control Signals
250
Power Control Signals
251
Interrupt Signals
253
CPU Interface Signals
254
ACE-Lite Interface Signals
255
Miscellaneous Signals
258
Interblock AXI4-Stream Interface Signals
260
Interdomain Signals
262
Interchip AXI4-Stream Interface Signals
262
Implementation-Defined Features
263
Revisions
265

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ARM CoreLink GIC-600AE Technical Reference Manual (268 pages)

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