Expansion Bus Global Control Register; Expansion Bus Global Control Register Field Description - Texas Instruments TMS320C6201 Reference Manual

Expansion Bus Registers
8.3.2

Expansion Bus Global Control Register

Figure 8–3. Expansion Bus Global Control Register
31 16 15
Reserved FMOD
R, +0 R,+x
Table 8–4. Expansion Bus Global Control Register Field Description
Field Description
FMOD FIFO mode set by boot-mode selection.
FMOD = 0: Glue is used for FIFO read interface in all XCE spaces operating in FIFO mode
FMOD = 1: Glueless read FIFO interface. If XCE3 is selected for FIFO mode, then XOE acts
as FIFO output enable and XCE3 acts as FIFO read enable. XOE is disabled in all other XCE
spaces regardless of MType setting.
XFCEN FIFO clock enable
XFCEN = 0: XFCLK held high
XFCEN = 1: XFCLK enabled to clock.
The FIFO clock enable cannot be changed while a DMA request to XCE space is active.
XFRAT FIFO clock rate
XFRAT = 00: XFCLK = 1/8 CPU clock rate
XFRAT = 01: XFCLK = 1/6 CPU clock rate
XFRAT = 10: XFCLK = 1/4 CPU clock rate
XFRAT = 11: XFCLK = 1/2 CPU clock rate
The FIFO clock setting cannot be changed while a DMA request to XCE space is active.
XARB Arbitration mode, set by boot-mode selection
XARB=0:
XARB=1:
8-8
The expansion bus global control register (shown in Figure 8–3, and de-
scribed in Table 8–4) configures parameters of the expansion bus common to
all interfaces.
14 13 12
XFCEN XFRAT
RW,+0 RW,+00
internal arbiter disabled
internal arbiter enabled
11 10
XARB
R,+x
Reserved
RW,+x
0