Receive Operation - Texas Instruments TMS320C6201 Reference Manual

Data Transmission and Reception
Figure 11–16. McBSP Standard Operation
CLK(R/X)
FS(R/X)
D(R/X)
A1 A0

Receive Operation

11.3.5.1
Figure 11–17. Receive Operation
CLKR
FSR
DR A1 A0
RRDY
RBR-to-DRR copy
(A)
11.3.5.2 Transmit Operation
11-34
B7 B6 B5
Figure 11–17 shows serial reception. Once the receive frame synchronization
signal (FSR) transitions to its active state, it is detected on the first falling edge
of the receiver's CLKR. The data on the DR pin is then shifted into the receive
shift register (RSR) after the appropriate data delay as set by RDATDLY. The con-
tents of RSR is copied to RBR at the end of every element on the rising edge of
the clock, provided RBR is not full with the previous data. Then, an RBR-to-DRR
copy activates the RRDY status bit to 1 on the following falling edge of CLKR. This
indicates that the receive data register (DRR) is ready with the data to be read
by the CPU or the DMA controller. RRDY is deactivated when the DRR is read
by the CPU or the DMA controller.
B7 B6 B5
Once transmit frame synchronization occurs, the value in the transmit shift
register, XSR, is shifted out and driven on the DX pin after the appropriate data
delay as set by XDATDLY. XRDY is activated after every DXR-to-XSR copy on
the following falling edge of CLKX, indicating that the data transmit register
(DXR) can be written with the next data to be transmitted. XRDY is deactivated
when the DXR is written by the CPU or the DMA controller. Figure 11–18 illus-
trates serial transmission. See section 11.3.7.4 for information on transmit op-
eration when the transmitter is pulled out of reset (XRST = 1).
B4 B3 B2 B1 B0
B4 B3 B2 B1 B0
Read of DRR RBR-to-DRR copy
(A)
C7
C7
Read of DRR
(B)
C6 C5
C6 C5
(B)