9.4.7
SDRAM Deactivation
Figure 9–22. SDRAM DCAB — Deactivate all Banks
Clock †
CEx
BE[3:0]
EA[15:2]
SDA10/
EA12
SDRAS
SDCAS
SDWE
† Clock=SDCLK for 'C6201/C6701.
Clock=CLKOUT2 for 'C6202.
Clock=ECLKOUT for 'C6211/C6711.
The SDRAM deactivation (DCAB) is performed after a hardware reset or when
INIT = 1 in the EMIF SDRAM control register. This cycle is also required by the
SDRAMs prior to REFR and MRS. On the 'C6201/C6202/C6701, a DCAB is
issued when a page boundary is crossed. During the DCAB command, SDA10
is driven high to ensure that all SDRAM banks are deactivated. Figure 9–22
shows the timing diagram for SDRAM deactivation.
DCAB
External Memory Interface
SDRAM Interface
9-35