Example Of The Expansion Bus Interface To Four 8-Bit Fifos; Addressing Scheme - Case When Expansion Bus Is Interfaced To Four 8-Bit Fifos - Texas Instruments TMS320C6201 Reference Manual

Figure 8–5. Example of the Expansion Bus Interface to Four 8-Bit FIFOs
Table 8–6. Addressing Scheme – Case When Expansion Bus is Interfaced to
Four 8-Bit FIFOs
Logical Address
FIFO #1 Address
FIFO #2 Address
FIFO #3 Address
FIFO #4 Address
Physical Address
Figure 8–5 illustrates how to interface four 8-bit FIFOs to the I/O port (memory
map for this case is described in Table 8–7). Figure 8–6 is an example of inter-
face between two 16-bit FIFOs and the I/O port.
XFCLK
XOE
XD[31:0]
XD[31:0]
XCE
XRE
XA[3]
XA[2]
A[31:6] A5
X X
X X
X X
X X
XA5
FIFO #1
CLK WEN
OE REN
D[7:0]
XD[7:0]
FIFO #2
CLK WEN
OE REN
D[7:0]
XD[15:8]
FIFO #3
CLK WEN
OE REN
D[7:0]
XD[23:16]
FIFO #4
CLK WEN
OE REN
D[7:0]
XD[31:24]
Decoder
A4 A3
X 0
X 0
X 1
X 1
XA4 XA3
Expansion Bus I/O Port Operation
A2 A1
0 0
1 0
0 1
1 1
XA2
Expansion Bus
A0
0
1
0
1
8-11