Hpi Block Diagram - Texas Instruments TMS320C6201 Reference Manual

Overview
Figure 7–3. HPI Block Diagram
7-4
Figure 7–3 is a simplified diagram of the 'C6201/'C6701 HPI.
The HPI provides 32-bit data to the CPU with an economical 16-bit external
interface by automatically combining successive 16-bit transfers. When the
host device transfers data through HPID, the DMA auxiliary channel accesses
the CPU's address space.
The 16-bit data bus, HD[15:0], exchanges information with the host. Because of
the 32-bit-word structure of the chip architecture, all transfers with a host consist
of two consecutive 16-bit halfwords. On HPI data (HPID) write accesses, the
HBE[1:0] byte enables select the bytes to be written. For HPIA, HPIC, and HPID
read accesses, the byte enables are not used. The dedicated HHWIL pin indi-
cates whether the first or second halfword is being transferred. An internal control
register bit determines whether the first or second halfword is placed into the most
significant halfword of a word. For a full word access, the host must not break the
first halfword/second halfword (HHWIL low/high) sequence of an ongoing HPI ac-
cess.
Host
Address
R/W
Data[15:0]
DATASTROBE
ALE
(if used)
BE
Ready
INTERRUPT
'C6201/'C6701
HCNTL[1:0]
HHWIL
HR/W
address
HD[15:0]
HDS1
HDS2
HCS
HAS
HBE[1:0]
HRDY
HINT
register
HPIA DMA
auxiliary
latches channel
Data
latches
Data
HPI
memory
control
controller
peripheral
(HPIC)
bus