Expansion Bus Host Port Operation
8.5 Expansion Bus Host Port Operation
Figure 8–13. Expansion Bus Host Port Interface Block Diagram
XHOLD
XHOLDA
XD[31:0]
XBE[3:0]
XRDY
XAS
XW/R
XBLAST
XBOFF
XCNTL
XCS
XWAIT
8-22
The expansion bus host port has two modes, which enable interfaces to exter-
nal processors, PCI bridge chips, or other external peripherals. These are the
synchronous host port mode and the asynchronous host port mode. The syn-
chronous host port mode can interface with minimum glue to PCI bridge chips
and many common microprocessors. The asynchronous host port mode en-
ables interfacing to genuine asynchronous devices.
The expansion bus host port block diagram is shown is Figure 8–13.
Bus
arbitration
MUX
Control
block
Using pull-up/down resistors on the data bus during reset sets the host port
operational mode, the DSP bootmode, and endianness.
'C6202
XBISA
address
latches
XBD data
latches
XBEA
address
latches
Expansion bus
memory
host port
controller
control
peripheral
registers
(XBGC, XBHC)
Enhanced
DMA
auxiliary
channel
Data
bus