Data Memory Organization (Tms320C6201 Revision 2) - Texas Instruments TMS320C6201 Reference Manual

Tms320c6000 series peripherals

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2.6 Internal Data Memory Organization

TMS320C6201 Revision 2

Table 2–2. Data Memory Organization (TMS320C6201 Revision 2)

First address

Last address

The following sections describe the memory organization of each device in the

'C6x generation of DSPs 'C6201 and 'C6701 devices.

The 64K bytes of internal data RAM are organized as one block of 64K bytes lo-

cated from address 8000 0000h to 8000 FFFFh. This block is organized as four

8K banks of 16-bit halfwords. Both the CPU and the DMA controller can simulta-

neously access data that resides in different banks. This organization allows the

two CPU data ports, A and B, to simultaneously access neighboring 16-bit data

elements inside the block without a resource conflict.

TMS320C6201/C6701 Program and Data Memory

Internal Data Memory Organization

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