Tms320C6201/C6202/C6701 Emif Prioritization Of Requests - Texas Instruments TMS320C6201 Reference Manual

9.8 Memory Request Priority
9.8.1 TMS320C6201/C6202/C6701 Memory Request Priority
Table 9–20. TMS320C6201/C6202/C6701 EMIF Prioritization of Requests
The 'C6201/C6202/C6701 EMIF has multiple requestors competing for the
interface. Table 9–20 summarizes the priority scheme that the EMIF uses in the
case of multiple pending requests. The priority scheme may change if the DMA
channel that is issuing a request through the DMA controller is of high priority.
This mode is set in the DMA controller by setting the PRI bit in the DMA channel
primary control register.
Once a requester (in this instance, the refresh controller is considered a
requester) is prioritized and chosen, no new requests are recognized until ei-
ther the chosen requester stops making requests or a subsequent higher priority
request occurs. In this case, all issued requests of the previous requester are
allowed to finish while the new requester starts making its requests.
If the arbitration bit of the EMIF global control register is set (RBTR8 = 1) and if
a higher priority requester needs the EMIF, the higher priority requester does not
gain control until the current controller relinquishes control or until eight word re-
quests have finished. If the arbitration bit is not set (RBTR8 = 0), a requester main-
tains control of the EMIF as long as it needs the EMIF or until a higher priority
requester requests the EMIF. When the RBTR8 is not set, the current controller
is interrupted by a higher priority requester regardless of the number of requests
that have occurred.
Priority
Highest
Lowest
Requestor PRI = 1
External hold
Mode register set
Urgent refresh
DMA controller
DMC
PMC
Trickle refresh
External Memory Interface
Memory Request Priority
Requestor PRI = 0
External hold
Mode register set
Urgent refresh
DMC
PMC
DMA controller
Trickle refresh
9-61